New memory technologies are enabling methods and systems as described herein that can enhance the user experience on mobile devices. More particularly, low power double data rate (LP-DDR) non-volatile memory has special characteristics which may promote such devices as the storage devices of choice for next generation handheld applications with promises of enabling high performance, improved security with even longer battery life time and more which have yet to be developed until now. JEDEC, the leading technology standards association for the solid-state industry hosted a standardization meeting in Munich, Germany, Aug. 27-31, 2007, focusing primarily on memory-related topics. Focus topics included LPDDR2 volatile dynamic read access memory (DRAM) and non-volatile memory (NVM). JEDEC, via its subcommittee JC-42.6, is defining a low power volatile and non-volatile memory standard (the latter described as “LPDDR2”), with the intent that the devices be bus-compatible, share the same operating frequencies and command protocol to facilitate controller design to accommodate the two device types on a single bus. Through this emerging standard, it is expected that an increase in the use of both volatile and non-volatile memory, in low power products, will result with a reduction in component counts and power.
Some applications will use LPDDR2 DRAM in combination with NAND flash memory on different buses. LPDDR2, however, has the unique property of being defined from the beginning to support both DRAM and nonvolatile memory on the same external memory bus. That allows systems using LPDDR2 memory to tap NVM to store the operating system and applications and to execute code directly out of the NVM device without downloading it into SD RAM first. Such an “execute in place” (XIP) architecture can provide significant advantages if implemented appropriately within the context of a handheld device.
Note that the PC memory road map looks to improve the PC memory performance in PC systems but sometimes at the detriment or without full consideration of the appropriate needs of an embedded system. PC memory density is also growing at a rate that is beyond the needs of some embedded systems. For these reasons, with each successive generation of PC memory, it is anticipated that usage will move from PC memory to LPDDR memory, even if those embedded systems do not necessarily need the low-power features offered by LPDDR.
Portable electronic computing systems have evolved over the years from ROMized embedded systems with a small amount of RAM to the now conventional flash and RAM based systems that more resemble general purpose computing systems, having the ability to store and execute various application programs. The conventional three main factors considered in the design of these systems are cost, size, and power consumption. In recent years, the desire to load and execute application programs and other functions has driven the design towards a general operating system with ability to operate web browsers, portable code such as Java™, and other applications. A Java operating environment for such devices has been standardized, and is known as Java 2 Micro Edition (J2ME).
Presently, conventional small computing devices, including smart cellular phones, personal digital assistants (PDAs), and palm-top computers, use a non-volatile flash memory (NVM) to store a boot kernel and other operating system elements, application software, user interface (UI) elements, and data. This conventional NVM is typically NAND type memory, which makes it block-addressable, and not byte-addressable like RAM or standard ROM. Being block addressable, it requires a dedicated bus to the application processor. Upon start-up, the processor must load the operating kernel from the NVM into RAM, which is connected to the application processor by a separate bus. This arrangement causes a significant load time upon turning on a device before a user can start operating the device. User's notice the long “power up” time while they wait for the device to be ready to use after pressing the “on” button. This wait time can be somewhat annoying, and in emergency situations waiting up to a minute may be critical.
Prior to using NAND flash NVM, other arrangements were used, including ROM. However, ROM doesn't allow the device to be updated, or applications to be installed, so that approach has been discarded. A NOR memory type flash NVM has been used, which is byte-addressable, connected to the same bus as “pseudo-RAM” and allowing “execute in place” (XIP) operation, but NOR type flash is significantly more expensive than NAND flash, and is not as durable (in lifetime write operations), so that approach also fell out of favor.
FIG. 1A shows a block schematic diagram 100 of an architecture for use in present conventional portable devices. A processor 102 is coupled to a NAND type flash NVM 104 via a first bus 106. The processor 102 is further coupled to a dynamic RAM (DRAM) 108 via a second bus 110. Upon powering up the device, the processor begins copying operating system and other instruction code from the flash to the DRAM, and indicated by arrow 112. Often the boot load copied to the DRAM is in compressed form to reduce memory footprint in the flash memory, thus requiring the boot kernel to be decompressed prior to instantiating it in the DRAM. This arrangement allows the device to have a general operating system to allow the addition of new application programs, as well as updates to the system software. It allows for use of less expensive NAND flash memory, as well as low cost DRAM type memory.
However, using two busses requires interface pins on the processor for each of the busses, causing the size of the processor integrated circuit to be larger than if just one bus were used. Furthermore, while the block-addressable NAND flash is less expensive, having to copy blocks from the flash, decompress them, and copy them to the DRAM takes a substantial amount of time. Therefore there is a need for an architecture that eliminates a bus interface, and reduces the start up time upon powering up the device.
Summaries of the Various Embodiments for Enhancing Handheld Device User Experience using NVM XIP Memories
As a result of the development of the enabling technology of NVM XIP memories with the LP-DDR2 interface, several novel and nonobvious examples have been created herein that enhance a user experience on handheld or wireless devices. Below is a non-exhaustive list of such concepts:                1. Method and System for Fast Boot-Up Based on Decomposition of the Application/GUI into a Kernel Binary Image that is Executable-in-Place from NVM Flash memory.        2. Method and System for Operating in Low-Power mode with Selection of Execute-in-Place Application Kernel running in Flash NVM and Duty Cycling external DRAM to reduce current drain.        3. Method for using Execute-in-Place Flash NVM for providing a high security device architecture.        4. Software Virus filter Algorithm for Multi-Media cellular phone or electronic device        5. Storage Algorithm for Multimedia Mobile Device        6. Method and System for Reducing Power Consumption in Mobile Electronic Devices using Execute-In-Place Non-Volatile Memory        
The terms “a” or “an,” as used herein, are defined as one or more than one. The term “plurality,” as used herein, is defined as two or more than two. The term “another,” as used herein, is defined as at least a second or more. The terms “including” and/or “having,” as used herein, are defined as comprising (i.e., open language). The term “coupled,” as used herein, is defined as connected, although not necessarily directly, and not necessarily mechanically.
The terms “program,” “software application,” and the like as used herein, are defined as a sequence of instructions designed for execution on a computer system. A program, computer program, or software application may include a subroutine, a function, a procedure, an object method, an object implementation, an executable application, an applet, a servlet, a source code, an object code, a shared library/dynamic load library and/or other sequence of instructions designed for execution on a computer system. The “processor” as described herein can be any suitable component or combination of components, including any suitable hardware or software, that are capable of executing the processes described in relation to the inventive arrangements.
Other embodiments, when configured in accordance with the inventive arrangements disclosed herein, can include a system for performing and a machine readable storage for causing a machine to perform the various processes and methods disclosed herein.